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Preliminary Technical Data
FEATURES
12-bit ADC, 1us per channel conversion time 6 Analog Input Channels, CM range 0.5V to 27.5V 6 Temperature Measurements Inputs. On Chip Voltage Regulator Cell Balancing Interface Daisy Chain Interface 3 ppm Reference Low Quiescent Current High Input Impedance Serial Interface with Alert Function 1 SPI interface for up to 300 channels On Chip Registers for Channel Sequencing VDD Operating Range 7.5V to 30V Temperature Range -40 oC to 105oC 48 lead LQFP and LFCSP Packages
Lithium Ion Battery Monitoring System AD7280
FUNCTIONAL BLOCK DIAGRAM
VDD SCLKhi SDINhi SDOUThi ALERThi CShi PDhi CNVSThi CB1 CB6
AD7280
Vin(6) Vin(5) Vin(4) Vin(3) Vin(2) Vin(1) Vin(0) MUX + -
DAIS Y CHAIN INTER FACE
CEL L BALANCING INTER FACE REGUL ATOR
VREG
DGND DVCC
+ -
12 BIT ADC
AVCC VDRIVE
VT(6) VT(5) VT(4) VT(3) VT(2) VT(1) VT TERM
CLOCK
CONTRO L LOGIC & SELF TEST SCLK SDIN SDO UT ALERT CS PD CNVST MASTER
VREF CREF
REFGND
2.5V REF
LIMIT REG SQN LOGIC DATA MEMO RY SPI INTER FACE
VSS
AGND
APPLICATIONS
Lithium Ion Battery Monitoring Nickel Metal Hydride Battery Monitoring
Figure 1
GENERAL DESCRIPTION
The AD72801 contains all the functions required for general purpose monitoring of stacked Lithium Ion batteries as used in Hybrid Electric Vehicles. The part has multiplexed analog input and temperature measurement channels for up to six cells of battery management. An internal 3-ppm reference is provided to drive the ADC. The ADC resolution is 12 bits with a 1 Msps throughput rate offering a 1s conversion time. The AD7280 operates from just one VDD supply which has a range of 7.5V to 30V (with an absolute max rating of 33V). The part provides 6 pseudo differential analog input channels to accommodate large common mode signals across the full VDD range. Each channel allows an input signal range, Vin(+) -Vin(-), of 0V to 5V. The input pins assume a series stack of 6 cells. In addition the part can accommodate 6 external sensors for temperature measurement. The AD7280 includes on chip registers which allow a sequence of channel measurements to be programmed to suit the applications requirements. The AD7280 also includes an Alert function which generates an interrupt output signal if the cell voltages exceed an upper or lower limit defined by the user. The AD7280 has balancing interface outputs designed to control external FET transistors to allow discharging of individual cells. The AD7280 includes a Built In Self Test feature which internally applies a known voltage to the ADC inputs. There is a daisy chain interface which allows up to 50 parts to be stacked without the need for individual device isolation. The AD7280 requires only one supply pin which takes 7mA under normal operation, while converting at 1 Msps. All this functionality is provided in a 48 pin LQFP or 48 pin LFCSP package operating over a temperature range of -40C to +105C.
1
Patents Pending
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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SDOUTlo ALERTlo
AD7280
SPECIFICATIONS
Table 1.
Parameter1 DC ACCURACY [Vin(0) to Vin(6)]2 Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Error Drift Offset Error Match Gain Error Gain Error Drift Gain Error Match ADC Unadjusted Error3 Total Unadjusted Error4 ANALOG INPUTS [Vin(0) to Vin(6)] Pseudo Differential Input Voltage Vin(n) - Vin(n-1) Absolute Input Voltage Common Mode Input Voltage DC Leakage Current Input Capacitance DC ACCURACY [VT1 to VT6]2 Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Error Drift Offset Error Match Gain Error Gain Error Drift Gain Error Match ADC Unadjusted Error5 Total Unadjusted Error6 ANALOG INPUTS (VT1 to VT6) Input Voltage Range Leakage Current Input Capacitance DYNAMIC PERFORMANCE Common Mode Rejection Ratio [CMRR] Min 12 1 1 1 3 1 1 2 1 0.05 0.08 0.07 0.1 Typ Max Unit Bits LSB LSB LSB ppm/oC LSB LSB ppm/oC LSB % % % %
Preliminary Technical Data
VDD = 7.5 V to 30 V, VSS = 0 V, DVCC = AVCC = VREG, VDRIVE = 2.7 V to 5.25 V, TA = -40oC to 105oC, unless otherwise noted
Test Conditions/Comments No Missing Codes
0.1 0.3 0.2 0.5
-40oC to 85oC -40oC to 105oC -40oC to 85oC -40oC to 105oC
1V VCM - VREF 0.5 70 15 3 12
2VREF VCM + VREF 27.5
V V V nA pF pF Bits LSB LSB LSB ppm/oC LSB LSB ppm/oC LSB % % % % V nA pF pF dB
CNVST pulse every 100ms When in track When in hold No Missing Codes
1 1 2 2 2 2 1.2 2 0.1 0.16 0.15 0.2 0 70 15 3 -75
0.2 0.6 0.4 1 2VREF
-40oC to 85oC -40oC to 105oC -40oC to 85oC -40oC to 105oC
CNVST pulse every 100ms When in track When in hold Up to 10kHz ripple frequency
Rev. PrD | Page 2 of 33
Preliminary Technical Data
Parameter1 REFERENCE Reference Voltage Reference Temperature Coefficient Output Voltage Hysteresis Long Term Drift Line Regulation Turn-On Settling Time REGULATOR OUTPUT Input Voltage Range Output Voltage VREG Output Current7 Line Regulation Load Regulation Output Noise Voltage Internal Short Protection Limit CELL BALANCING OUTPUTS8 Output High Voltage, VOH Output Low Voltage, VOL CB1 Output ramp up time9 CB1 Output ramp down time10 CB2-CB6 Output ramp up time11 CB2-CB6 Output ramp down time12 LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance Output Coding POWER REQUIREMENTS VDD During Conversion IDD Data Readback IDD Cell Balancing mode IDD Software Powerdown Mode IDD Full Powerdown Mode IDD Min 2.495 Typ 2.5 3 50 100 15 5 7.5 4.75 30 5.25 Max 2.505 15 Unit V ppm/C ppm ppm/1000 Hours ppm/V ms V V mA mV/V mV/mA uV mA V V us ns us us Test Conditions/Comments VREF @ 25oC -40 oC to +85 oC -40 oC to +85 oC
AD7280
AVDD =7.5V VREF = 10uF , CREF = 100nF
5 1 0.4 2.5 700 20 5 5 50 350 330
For a 10 Ohm short For a 80pF load, ISOURCE = 40 nA For a 80pF load For a 80pF load For a 80pF load For a 80pF load
4 0
5.25
VDRIVE - 0.2 0.4 1 10 VDRIVE - 0.2 0.4 1 5 Straight natural binary 7.5 7 4 30 10 8 2 1 4
V V A pF V V A pF ISOURCE = 200 A ISINK = 200 A
V mA mA mA mA A VDD = 30 V VDD = 30 V VDD = 30 V VDD = 30 V VDD = 30 V
Rev. PrD | Page 3 of 33
AD7280
Parameter1 POWER DISSIPATION During Conversion Full Powerdown Mode Min Typ Max 300 120 Unit mW W
Preliminary Technical Data
Test Conditions/Comments VDD = 30 V VDD = 30 V
1 2 3
Temperature range is -40C to +105C. For dc accuracy specifications, the LSB size for cell voltage measurements is (2VREF-1V)/4096, the LSB size for temperature measurements is 2VREF/4096. ADC Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the Vin0 to Vin6 input channels. 4 Total Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the Vin0 to Vin6 input channels as well as the temperature coefficient of the 2.5V reference. 5 ADC Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the VT input channels. 6 Total Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the VT input channels as well as the temperature coefficient of the 2.5V reference. 7 This spec outlines the regulator output current which is available for external use, that is, it does not include the regulator current already being used by the AD7280. 8 CB output can be set to 0V or 5V with respect to negative terminal of cell being balanced. 9 CB1 output ramp up time is defined from the rising edge of the CS command until the CB output exceeds 4V with respect to negative terminal of cell being balanced. 10 CB1 output ramp down time is defined from the falling edge of the CS command until the CB output falls below 50mV with respect to negative terminal of cell being balanced. This specification is defined from the falling edge of CS as any CB outputs which on are switched off for the duration of a CS low pulse and will be switched back on following the rising edge of that CS pulse. 11 CB2 to CB6 output ramp up time is defined from the rising edge of the CS command until the CB output exceeds 4V with respect to negative terminal of cell being balanced. 12 CB2 to CB6 output ramp down time is defined from the falling edge of the CS command until the CB output falls below 50mV with respect to negative terminal of cell being balanced. This specification is defined from the falling edge of CS as any CB outputs which on are switched off for the duration of a CS low pulse and will be switched back on following the rising edge of that CS pulse.
TIMING SPECIFICATIONS
VDD = 7.5 V to 30 V, VSS = 0 V, DVCC = AVCC = VREG, VDRIVE = 2.7 V to 5.25 V, TA = -40oC to 105oC, unless otherwise noted.1 Table 2.
Parameter tCONV tDELAY fSCLK tQUIET t1 t2 t3 t4 t5 t62 t7 t8 t9 t10 t11 Limit at TMIN, TMAX 2.7 V VDRIVE < 4.75 V 4.75 V VDRIVE 5.25 V 610 610 50 50 10 1 200 10 10 10 5 3 20 7 0.3 x tSCLK 0.3 x tSCLK 10 10 10 1 200 10 10 10 5 3 14 7 0.3 x tSCLK 0.3 x tSCLK 10 10 Unit ns max ns max kHz min MHz max ns min ns min ns min ns max ns min ns min ns max ns min ns min ns min ns min ns max Test Conditions/Comments ADC Conversion time Propogation delay between adjacent parts on the Daisy Chain Frequency of serial read clock Minimum quiet time required between the end of serial read and the start of the next conversion Minimum CONVST low pulse CS falling edge to SCLK rising edge Delay from CS falling edge until SDO is three-state disabled SDI setup time prior to SCLK falling edge SDI hold time after SCLK falling edge Data access time after SCLK falling edge SCLK to data valid hold time SCLK high pulse width SCLK low pulse width CS rising edge to SCLK rising edge CS rising edge to SDO high impedance
1
2
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. The time required for the output to cross 0.4 V or 2.4 V.
Rev. PrD | Page 4 of 33
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted Table 3.
Parameter VDD to AGND VSS to AGND Vin0 to Vin5 Voltage to AGND Vin6 Voltage to AGND CB1 Output to AGND CB2 to CB6 Output to AGND VT1 to VT6 Voltage to AGND AVCC to AGND, DGND DVCC to AVCC DVCC to DGND VDRIVE to AGND AGND to DGND Digital Input Voltage to DGND Digital Output Voltage to GND Operating Temperature Range Storage Temperature Range Junction Temperature LQFP Package JA Thermal Impedance JC Thermal Impedance LFCSP Package JA Thermal Impedance JC Thermal Impedance Pb-free Temperature, Soldering Reflow Rating -0.3 V to +33 V -0.3 V to +0.3 V VSS - 0.3 V to VDD + 0.3 V VDD to VDD + 1 V -0.3 V to DVCC + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to AVCC + 0.3 V -0.3 V to +7 V -0.3 V to +0.3 V -0.3 V to +7 V -0.3 V to DVCC -0.3 V to +0.3 V -0.3 V to VDRIVE + 0.3V -0.3 V to VDRIVE + 0.3V -40C to +105C -65C to +150C 150C 76.2C/W 17C/W 54C/W 15C/W 260(+0)C
AD7280
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrD | Page 5 of 33
AD7280
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
Preliminary Technical Data
CNVSThi
ALERThi
REFGND
SCLKhi
SDOhi
CREF
VREF
SDIhi
PDhi
CShi
VT1
VT2
48 47 46 45 44 43 42 41 40 39 38 37
VIN6 CB6 VIN5 CB5 VIN4 CB4 VIN3 CB3 VIN2 CB2 VIN1 CB1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN 1
36 VT3 35 VT4 34 VT5 33 VT6
48 47 46 45 44 43 42 41 40 39 38 37
PDhi CShi SCLKhi SDOhi CNVSThi SDIhi ALERThi REFGND VREF CREF VT1 VT2
VIN6 CB6
1 2
PIN 1 INDICATOR
AD7280
TOP VIEW
32 VTTERM 31 AGND 30 AVCC 29 VDRIVE 28 ALERTlo 27 ALERT 26 SDO
00000-000
25 SDOlo
CNVST
MASTER
Figure 2.
Table 4.
Pin No. 1, 3, 5, 7, 9, 11, 13 Mnemonic Vin6 to Vin0 Description Analog Input 0 to Analog Input 6. Analog input 0 should be connected to the base of the series connected battery cells. Analog Input 1 should be connected to the top of cell 1, Analog Input 2 should be connected to the top of cell 2, etc. The Analog Inputs are multiplexed into the on-chip track-and-hold allowing the potential across each cell to be measured. Cell Balance Outputs. These provide a voltage output which can be used to supply the gate drives of a cell balancing transistor network. Each CB(n) output provides a 5V voltage output referenced to the absolute voltage of Cell(n-1). Voltage Input. In an application with 2 or more AD7280s Daisy Chained the MASTER pin of the AD7280 connected directly to the DSP or uP should be connected to the VDD supply pin through a 10kOhm resistor. The MASTER pin on the remaining AD7280s in the application should be tied to their respective VSS supply pins through 10kOhm resistors. Power down Input. This input is used to power down the AD7280. When acting as master the PD input is supplied from the DSP/uP. When acting as a slave on the Daisy Chain the PD input should be connected to the PDhi output of the AD7280 immediately below it in potential in the Daisy Chain. This input can also be tied to VCC and the power down initiated through the serial interface. Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure AD7280. The supply must be greater than a minimum voltage of 7.5 V. In an application monitoring the cell voltages of up to 6 series connected battery cells the supply voltage may be supplied directly from the cell with the highest potential. The maximum voltage which can be applied between VDD and VSS is 30V. Place 10 F and 100 nF decoupling capacitors on the VDD pin. Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure of the AD7280. This input should be at the same potential as the AGND voltage. Analog Voltage output, 5V. The internally generated VREG voltage, which provides the supply voltage for the ADC core, is available on this pin for use external to the AD7280. Place 10 F and 100 nF decoupling capacitors on the VREG pin. Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled to DGND. Place 100 nF decoupling capacitors on the DVCC pin. The DVCC supply pin should be connected to the VREG output
Rev. PrD | Page 6 of 33
2, 4, 6, 8, 10, 12 14
CB6 to CB1
MASTER
15
PD
16
VDD
17 18
VSS VREG
19
DVCC
VIN0 MASTER PD VDD VSS VREG DVCC DGND CS SCLK SDI CNVST
DGND
VREG
DVCC
VDD
SCLK
VIN0
VSS
SDI
PD
CS
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3.
00000-000
VIN5 3 CB5 4 VIN4 5 CB4 6 VIN3 7 CB3 8 VIN2 9 CB2 10 VIN1 11 CB1 12
AD7280
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25
VT3 VT4 VT5 VT6 VTTERM AGND AVCC VDRIVE ALERTlo ALERT SDO SDOlo
Preliminary Technical Data
20 21 DGND CS
AD7280
22
SCLK
23
SDI
24
CNVST
25
SDOlo
26
SDO
27
ALERT
28
ALERTlo
29
VDRIVE
30
AVCC
31
AGND
32 33 to 38 39 40
VTTERM VT6 to VT1 CREF VREF
41 42
REFGND ALERThi
Digital Ground. Ground reference point for all digital circuitry on the AD7280. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Chip select Input. When acting as a master, that is the Master pin of the AD7280 is connected to VDD, the CS input is used to frame the input and output data on the SPI. The CS input also frames the input and output data on the Daisy Chain Interface when the MASTER input of the AD7280 is connected to VSS. Serial Clock Input. When acting as master the SCLK input is supplied from the DSP/uP. When acting as a slave on the Daisy Chain this input should be connected to the SCLKhi output of the AD7280 immediately below it in potential in the Daisy Chain. Serial Data Input. Data to be written to the on-chip registers is provided on this input and is clocked into the AD7280 on the falling edge of SCLK. When acting as master this is the data input of the SPI interface. When acting as a slave on the Daisy Chain this input acepts data from the SDOhi output of the AD7280 immediately below it in potential in the Daisy Chain. Convert Start Input. The conversion is initiated on the falling edge of CONVST. When acting as master the CNVST pulse is supplied from the DSP/uP. When acting as a slave on the Daisy Chain this input should be connected to the CNVSThi output of the AD7280 immediately below it in potential in the Daisy Chain. This input can also be tied to VCC and the conversion initiated through the serial interface. Serial Data Output in Daisy Chain mode. This output should be connected to the SDIhi input of the AD7280 immediately below it in potential on the Daisy Chain. The data from each AD7280 in the Daisy Chain will be passed through the SDOlo outputs and SDIhi inputs of each AD7280 in the chain and supplied to the uP/DSP through the SDO output of the master AD7280. Serial Data Output. The conversion output data or the register output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input, and 24 SCLKs are required to access the data. The data is provided MSB first. In a Daisy Chain application the SDO output of the master AD7280 should be connected to the uP/DSP. The SDO outputs of the remaining AD7280s in the chain should be terminated to VSS through a 1k resistor. The data from each AD7280 in the Daisy Chain will be passed through the SDOlo outputs and SDIhi inputs of each AD7280 in the chain and supplied to the uP/DSP through the SDO output of the master AD7280. 24 SCLKs are required for each AD7280 in the chain to access the data. Digital Output. Flag to indicate over voltage, under voltage, over temperature or under temperature. The ALERT output of the master AD7280 should be connected to the uP/DSP. The ALERT outputs of the remaining AD7280s in the chain should be be terminated to VSS through a 1k resistor.. Alert Output in Daisy Chain mode. The alert signal from each AD7280 in the Daisy Chain will be passed through the ALERTlo outputs and ALERThi inputs of each AD7280 in the chain and supplied to the uP/DSP through the ALERT output of the master AD7280. This input should be connected to the ALERThi input of the AD7280 immediately below it in potential on the Daisy Chain. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different to the voltage at AVCC and DVCC, but should never exceed either by more than 0.3 V. Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC core. The AVCC and DVCC voltages should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled to AGND. Place 100 nF decoupling capacitors on the AVCC pin. The AVCC supply pin should be externally connected to the VREG output. Analog Ground. Ground reference point for all analog circuitry on the AD7280. This input should be at the same potential as the base of the series connected battery cells. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Thermistor termination resistor input. Voltage temperature input from potential divider with thermistor. A 100 nF decoupling capacitor to REFGND should be placed on this pin. Reference Output. The on-chip reference is availble on this pin for use external to the AD7280. The nominal internal reference voltage is 2.5V, which appears at the pin. A 10 F decoupling capacitor to REFGND is recommended on this pin. Reference Ground. This is the ground reference point for the internal bandgap reference circuitry on the AD7280. The REFGND voltage should be at the same potential as the AGND voltage. Alert Input in Daisy Chain mode. Flag to indicate over voltage, under voltage, over temperature or under temperature in Daisy Chain mode. The alert signal from each AD7280 in the Daisy Chain will be passed through the ALERTlo outputs and ALERThi inputs of each AD7280 in the chain and supplied to the uP/DSP through the ALERT output of the master AD7280. This input should be connected to the ALERTlo output of the AD7280 immediately above it in potential on the Daisy Chain.
Rev. PrD | Page 7 of 33
AD7280
43 SDIhi
Preliminary Technical Data
Serial Data Input in Daisy Chain mode. The data from each AD7280 in the Daisy Chain will be passed through the SDOlo outputs and SDIhi inputs of each AD7280 in the chain and supplied to the uP/DSP through the SDO output of the master AD7280. This input should be connected to the SDOlo output of the AD7280 immediately above it in potential on the Daisy Chain. Conversion Start Output in Daisy Chain mode. The convert start signal from the uP/DSP supplied to the CNVST input of the Master AD7280 is passed through each AD7280 by means of the CNVST input and the CNVSThi output. This output should be connected to the CNVST pin of the AD7280 immediately above it in potential on the Daisy Chain. Serial Data Output in Daisy Chain mode. The Serial Data input from the uP/DSP supplied to the SDI input of the Master AD7280 is passed through each AD7280 by means of the SDI input and the SDOhi output. This output should be connected to the SDI input of the AD7280 immediately above it in potential on the Daisy Chain. Serial Clock Output in Daisy Chain mode. The clock signal from the uP/DSP supplied to the SCLK input of the Master AD7280 is passed through each AD7280 by means of the SCLK input and the SCLKhi output. This output should be connected to the SCLK input of the AD7280 immediately above it in potential in the Daisy Chain. Chip select Output in Daisy Chain mode. The chip select signal from the uP/DSP supplied to the CS input of the Master AD7280 is passed through each AD7280 by means of the CS input and the CShi output. This output should be connected to the CS input of the AD7280 immediately above it in potential on the Daisy Chain. Power down Output in Daisy Chain mode. The power down signal from the uP/DSP supplied to the PD input of the Master AD7280 is passed through each AD7280 by means of the PD input and the PDhi output. This output should be connected to the PD pin of the AD7280 immediately above it in potential on the Daisy Chain.
44
CNVSThi
45
SDOhi
46
SCLKhi
47
CShi
48
PDhi
Rev. PrD | Page 8 of 33
Preliminary Technical Data TERMINOLOGY
Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition). Offset Code Error This applies to straight binary output coding. It is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal, that is, AGND + 1 LSB. Gain Error This applies to straight binary output coding. It is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is, 4 x VREF - 1 LSB, 2 x VREF - 1 LSB, VREF - 1 LSB) after adjusting for the offset error. ADC Unadjusted Error ADC Unadjusted Error includes integral nonlinearity errors, offset and gain errors of the ADC and measurement channel. Total Unadjusted Error (TUE) This is the maximum deviation of the output code from the ideal. Total Unadjusted Error includes integral nonlinearity errors, offset and gain errors and reference drift. Offset Error Match This is the difference in zero code error across all 6 channels. Gain Error Match The difference in gain error across all 6 channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of a conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 LSB, after the end of conversion. Common Mode Rejection Ration (CMRR) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV sine wave applied to the common-mode voltage of the Vin(n) and Vin(n-1) frequency, fS, as CMRR (dB) = 10 log (Pf/PfS)
AD7280
where Pf is the power at frequency f in the ADC output, and PfS is the power at frequency fS in the ADC output. Power Supply Rejection Ration (PSRR) Variations in power supply affect the full-scale transition but not the converter's linearity. PSRR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the maximum and minimum reference output voltage (VREF) measured at TMIN, T(25C), and TMAX. It is expressed in ppm/C using the following equation:
TCVREF ( ppm / C ) = VREF ( Max) - VREF ( Min) x 10 6 VREF (25C ) x (TMAX - TMIN )
where: VREF(Max) = Maximum VREF at TMIN, T(25C), or TMAX VREF(Min) = Minimum VREF at TMIN, T(25C), or TMAX VREF(25C) = VREF at +25C TMAX = +85C TMIN = -40C Output Voltage Hysteresis Output voltage hysteresis, or thermal hysteresis, is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either T_HYS+ = +25C to TMAX to +25C T_HYS- = +25C to TMIN to +25C It is expressed in ppm using the following equation:
VHYS ( ppm) =
VREF (25C ) - VREF (T _ HYS) x 10 6 VREF (25C )
where: VREF(25C) = VREF at 25C VREF(T_HYS) = Maximum change of VREF at T_HYS+ or T_HYS-.
Rev. PrD | Page 9 of 33
AD7280
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7280 is a Lithium Ion battery monitoring chip with the ability to monitor the voltage and temperature of 6 series connected battery cells. The AD7280 also provides an interface which can be used to control transistors for cell balancing. The VDD and VSS supplies required by the AD7280 can be taken from the upper and lower voltages of the series connected battery cells. An internal VREG rail is generated from the supply voltage which provides power for the ADC and the internal interface circuitry. This VREG voltage is available on an output pin for use external to the AD7280. The AD7280 consists of a high voltage input multiplexer, a low voltage input multiplexer and a 12 bit ADC. The high voltage multiplexer allows up to 6 series connected Lithium Ion battery cells to be measured. The low voltage multiplexer allows the temperature of each cell to be measured. A single CNVST signal is required to initiate conversions on all 12 channels, that is 6 voltage and 6 temperature channels. Alternatively the conversion can be initiated through the rising edge of CS on the SPI interface. Each conversion result is stored in a results register (See Register section). On power-up, the CNVST signal is the default option, this can be changed by writing to the CONTROL register. The default sequence of conversions completed following the CNVST signal, or software convert start, is all 6 voltage channels followed by all 6 temperature channels. Two further conversion sequences may be selected by the user, 6 voltage channels followed by 3 temperature channels or just 6 voltage channels. The conversion sequence may be selected by writing to the CONTROL register. Each voltage and temperature measurement requires a minimum of 1us to acquire and complete a conversion. Depending on the external components connected to the analog inputs of the AD7280 additional acquisition time may be required. A higher acquisition time may be selected through the CONTROL register. The user may also select the averaging option through the CONTROL register. This option allows the user to complete 2, 4 or 8 averages on each cell voltage and cell temperature measurement. The averaged conversion results are stored in the results registers. On power-up the default combined acquisition and conversion time will be 1us, with the averaging register set to zero, that is a single conversion per channel. The results of the voltage and temperature conversions are read back via the 4 wire Serial Peripheral Interface. The SPI interface is also used to write to and read data from the internal registers. The AD7280 features an ALERT function which is triggered if the voltage conversion results or the temperature conversion results exceed the maximum and minimum voltage thresholds
Rev. PrD | Page 10 of 33
Preliminary Technical Data
selected by the user. The threshold levels are selected by writing to the internal registers. The AD7280 provides 6 analog output voltages which can be used to control external transistors as part of a cell balancing circuit. Each Cell Balance output provides a 0V or 5V voltage, with respect to the potential on base of each individual cell, which can be applied to the gate of the external cell balancing transistors. The AD7280 features a daisy chain interface. Individual AD7280s can monitor the cell voltages and temperatures of 6 cells, a chain of AD7280s can be used to monitor the cell voltages and temperatures of a larger number of cells. The conversion data from each AD7280 in the chain passes to the system controller via a single standard serial interface. Control data can similarly be passed via the standard serial interface up the chain to each individual AD7280s The AD7280 includes an on-chip 2.5V reference. The reference voltage is available for use external to the AD7280.
CONVERTER OPERATION
The AD7280 consists of a high voltage input multiplexer, a low voltage input multiplexer and a 12 bit ADC. The high voltage multiplexer selects which pair of analog inputs, Vin0 to Vin6, are to be converted. The voltage of each individual cell is measured by converting the difference between adjacent analog inputs, that is, Vin1 - Vin0, Vin2 - Vin1, etc. This is illustrated in Figure 4 and Figure 5. The conversion results for each cell may be accessed after the programmed conversion sequence is complete. The second multiplexer selects which voltage temperature input, VT1 to VT6, is to be converted. The conversion results for each cell may be accessed after the programmed conversion sequence is complete.
Vin6 Vin5 Vin4 Vin3 Vin2 Vin1 Vin0
ADC Vin+
ADC Vin-
Figure 4. MUX Configuration During Vin1-Vin0 Sampling
Preliminary Technical Data
Vin6 Vin5 Vin4 Vin3 Vin2 Vin1 Vin0
ADC Vin+
AD7280
ANALOG INPUT STRUCTURE
Figure 8 shows the equivalent circuit of the analog input structure of the AD7280. The two diodes provide ESD protection. The resistors are lumped components made up of the on-resistance of the input multiplexer and the track-andhold switch. The value of these resistors is typically about 300. Capacitor C1 can primarily be attributed to pin capacitance while Capacitor C2 is the sampling capacitor of the ADC. The total lumped capacitance of C1 and C2 is approximately 13 pF.
VDD D C2
ADC Vin-
Figure 5. MUX Configuration During Vin2-Vin1 Sampling
The ADC is a 12-bit successive approximation analog-to-digital converter. The converter is composed of a comparator, SAR, some control logic and 2 capacitive DACs. Figure 6 shows a simplified schematic of the converter. During the acquisition phase switches SW1, SW2 and SW3 are closed. The sampling capacitor array acquires the signal on the input during this phase.
CAPACITIVE DAC B VIN+ VIN- CS SW3 COMPARATOR
VIN+ C1 D VSS VDD D VIN- C1 D VSS
R1
R1
C2
A SW1 A SW2 B CS
CONTROL LOGIC
Figure 8. Equivalent Analog Input Circuit
CAPACITIVE DAC
TRANSFER FUNCTION
The output coding of the AD7280 is straight binary. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent on whether the voltage or temperature inputs are being measured. The analog input range of the voltage inputs is 1V to 5V, the analog input range of the temperature inputs is 0V to 5V. The ideal transfer characteristic is shown in Figure 9.
Table 5. LSB Sizes for Each Analog Input Range
Selected inputs Voltage Temperature Input Range 1 V to 5 V 0 V to 5 V Full-Scale Range 4 V/4096 5 V/4096 LSB Size 976 V 1.22 mV
Figure 6. ADC Configuration During Acquisition Phase
When the ADC starts a conversion (Figure 7), SW3 opens and SW1 and SW2 move to position B, causing the comparator to become unbalanced. The control logic and capacitive DACs are used to add and subtract fixed amounts of charge to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. This output code is then stored in the appropriate register for the input that has been converted.
CAPACITIVE DAC B VIN+ VIN- CS SW3
ADC CODE
111...111 111...110
COMPARATOR CONTROL LOGIC
111...000 011...111
A SW1 A SW2 B CS
Figure 7. ADC Configuration During Conversion Phase
Rev. PrD | Page 11 of 33
Figure 9. Transfer Characteristic
04852-022
CAPACITIVE DAC
000...010 000...001 000...000 1V + 1LSB 5V - 1LSB AGND + 1LSB 5V - 1LSB ANALOG INPUT 4V INPUT RANGE 5V INPUT RANGE
04852-024
AD7280
TYPICAL CONNECTION DIAGRAMS
The AD7280 can be used to monitor 6 battery cells connected
Preliminary Technical Data
in series. A typical configuration for a 6 cell battery monitoring application is shown in Figure 10.
0.1F
10F
Vin6 CB6 Vin5
10k
VDD MASTER VREG DVCC AVCC VDRIVE
0.1uF 0.1uF 10uF
CB5 Vin4 VREF CREF CB4
Vin3
10uF
OPTIONAL INTERFACE PINS
AD7280
ALERT CNVST PD SDO SCLK SDI CS
VSS
0.1uF
CB3 Vin2
CB2
Vin1
C/P
CB1 Vin0
4 WIRE SPI INTERFACE
Figure 10. AD7280 Configuration Diagram for 6 Battery Cells
Lithium Ion Battery applications require a significant number of individual cells to provide the required output voltage. Individual AD7280s can monitor the cell voltages and temperatures of 6 series connected cells. The Daisy Chain Interface of the AD7280 allows each individual AD7280 to communicate with another AD7280 immediately above or below it. The daisy chain interface allows the AD7280s to be electrically connected to the battery management chip, as shown in Figure 11 without the need for individual isolation between each AD7280.
application. When using a chain of AD7280s it is also recommended that a 100kOhm series resistor be placed on the PD input. This is recommended to limit current into the PD pin in the event that the uP/DSP or isolators are connected before the supplies of the master AD7280. Please refer to the Daisy Chain Interface Section for a more detailed description of the Daisy Chain Interface. In an application which includes a safety mechanism, designed to open circuit the Battery Stack, additional isolation will be required between the AD7280 above the break point and the battery management chip.
Daisy Chain Connection Diagram
As shown in Figure 11 external diodes have been included on the VDD supply to each AD7280 and on each Daisy Chain signal between adjacent AD7280's. These diodes, in combination with the 10k series resistors on the analog inputs, are recommended to prevent damage to the AD7280 in the event of an open circuit in the battery stack. It is also recommended that a zener diode be placed across the supplies of each AD7280 as shown in Figure 11. This will prevent an over voltage across the supplies of each AD7280 during the initial connection of the daisychain of AD7280s to the battery stack. A voltage rating of 33V is suggested for this zener diode but lower values may also be used to suit the
EMC Considerations
In addition to the standard decoupling capacitors, C2n and C3n, as shown in Figure 11, it is also recommended that an option for additional capacitors, C1n and C4n, be included in the circuit to increase immunity to Electomagnetic Interference. These capacitors, placed on either side of the VDD protection diode, would be used to decouple the VDD supply of each AD7280 with respect to system ground., that is the ground of the master AD7280 in the daisychain.
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Preliminary Technical Data
It is recommended that ferrite beads be included on the battery connections to the VDD and VSS supplies. It is also recommended that pull-down resistors should be used on the
AD7280
ALERT and SDO outputs on each of the slave parts in the AD7280 daisychain.
VDDn C2n C1n 0.1uF 0.1uF C3n 10uF C4n 0.1uF
CShi SCLKhi SDOhi CNVSThi SDIhi ALERThi
PDhi
VDD(n-1) 10k 100nF
VDD Vin6 Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 VSS
VREG DVCC AVCC VDRIVE ALERT SDO MASTER
0.1uF
10uF
AD7280
1k 1k 10k 10uF
CS SCLK SDi CNVST SDOlo ALERTlo
VREF CREF
0.1uF
VDD(n-1) VDD1 C11 0.1uF C21 0.1uF VDD0 10k 100nF Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 VSS VDD0 C10 0.1uF 10uF C30 10k
Vin6
PD
CS SCLK SDi CNVST SDOlo ALERTlo
PD
VDD(n-1)
10uF C31
C41 0.1uF VDD Vin6
CShi SCLKhi SDOhi CNVSThi SDIhi ALERThi
PDhi
VREG DVCC AVCC VDRIVE 0.1uF
10uF
AD7280
ALERT SDO MASTER VREF CREF
1k 1k 10k 10uF 0.1uF
VDD0 C40 0.1uF
CShi SCLKhi SDOhi CNVSThi
10k
PDhi
MASTER
SDIhi ALERThi
VDD
VREG DVCC AVCC VDRIVE 0.1uF 10uF OPTIONAL INTERFACE PINS
100nF
Vin5 Vin4 Vin3 Vin2 Vin1 Vin0
AD7280
VSS VSS0
CREF VREF
ALERT CNVST PD SDO SCLK SDI CS
100k
C/P
SDOlo ALERTlo
4 WIRE SPI INTERFACE 0.1uF 10uF
Figure 11. AD7280 Daisy Chain Configuration
VDRIVE
The AD7280 also has a VDRIVE feature to control the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, in
the recommended configuration the AD7280 is operated with a VCC of 5 V, however the VDRIVE pin could be powered from a 3 V supply, allowing a large dynamic range with low voltage digital processors.
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AD7280
REFERENCE
The internal reference is temperature compensated to 2.5 V 5 mV. The reference is trimmed to provide a typical drift of 3 ppm/C . The internal reference circuitry consists of a 1.2 V band gap reference and a reference buffer. The AD7280 internal reference is available at the VREF pin. The VREF pin should be decoupled to AGND using a 10 F, or greater, ceramic capacitor. The CREF pin should be decoupled to AGND using a 0.1 F, or greater, ceramic capacitor. The internal reference is capable of driving an external load of up to 10kOhms.
Preliminary Technical Data
Each voltage and temperature conversion requires a minimum of 1us to acquire and convert the cell voltage or temperature voltage input. For example. when D15 and D14 are set to zero the falling edge of CNVST will trigger a series of 12 conversions. This will require a minimum of 12s to convert all selected measurements. If no temperature conversions are required then Bits D15 and D14 would be set to 10. In this case the conversion request will trigger a series of 6 conversions, requiring a minimum of 6s.
Track-and-Hold
The track-and-hold on the analog input of the AD7280 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. Following a completed conversion the AD7280 enters its tracking mode. The time required to acquire an input signal depends on how quickly the sampling capacitor is charged. This in turn will depend on the input impedance and any external components placed on the analog inputs. The default acquisition time of the AD7280 on initial power up is 400 ns. This can be increased in steps of 400ns to 1.6 us to provide flexibility in selecting external components on the analog inputs. The acquisition time is selected by writing to bits D6 and D5 in the CONTROL register.
Table 7.Analog Input Acquisition Time.
D6 to D5 00 01 10 11 Acquisition Time 400 ns 800 ns 1.2 s 1.6 s
CONVERTING CELL VOLTAGES AND TEMPERATURES
A conversion may be initiated on the AD7280 using either the CNVST input or the serial interface. A single CNVST signal is required to initiate conversions on all 12 channels, that is 6 voltage and 6 temperature channels. Alternatively the conversion can be initiated through the rising edge of CS on the SPI interface. When using the CNVST input the falling edge of CNVST places the track and hold on the voltage inputs Vin0 and Vin1, that is across Cell 1, into hold mode and initiates the conversion. At the end of the first conversion the AD7280 generates an internal End of Conversion signal. This internal EOC will select the next cell voltage inputs for measurement though the multiplexer, that is Vin1 and Vin2. The track-and-hold circuit will acquire the new input voltage and a second internal convert start signal is generated which places the track-and-hold into hold mode and initiates the conversion. This process is repeated until all the selected voltage and temperature cell inputs have been converted. Please refer to Figure 12 and Figure 13. Note, once all selected conversions have been completed voltage inputs Vin0 and Vin1 are again selected through the multiplexer and the voltage across Cell 1 is acquired in preparation for the next conversion request. By setting bits D15 and D14 in the control register the voltage and temperature cells to be converted are selected. There are four options available.
Table 6. Voltage and Temperature Cell Selection
D15 to D14 00 01 10 11 Voltage inputs 1 to 6 1 to 6 1 to 6 ADC Self Test Temperature Inputs 1 to 6 1, 3 & 5 None None
The acquisition time required is calculated using the following formula: tACQ = 10 x ((RSOURCE + R) C) where: C is the sampling capacitance, the value of the sampling capacitor, 18pF R is the resistance seen by the track-and-hold amplifier looking at the input, 500. RSOURCE should include any extra source impedance on the analog input.
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Preliminary Technical Data
t1
CNVST
AD7280
tACQ
tCONVERT
INTERNAL ADC CONVERSIONS VOLT 1 VOLT 2 VOLT 3
tCONVERT
TEMP 6
Figure 12. ADC conversions on the AD7280
t1
CNVST
tQUIET
INTERNAL ADC CONVERSIONS V1 V2 V3 T6 V1 V2
CS
SERIAL READ OPERATION 1 24 x NO. OF CONVERSIONS
Figure 13. ADC conversions & Readback on the AD7280
Converting Cell Voltages and Temperatures with a chain of AD7280s
The AD7280 provides a daisy chain interface which allows up to 50 parts to be stacked without the need for individual isolation. One feature of this daisychain interface is the ability to initiate conversions on all parts in the daisychain stack with a single conversion start command. The conversion can be initiated through a single CNVST pulse or through the rising edge of CS on the SPI interface. The convert start command is transferred up the daisychain, from the master device, to each AD7280 in turn. The delay time between each AD7280 is tDELAY, as outlined in Figure 14. The maximum delay between the start of conversions on the master AD7280 and the last AD7280 device in the chain can be determined by multiplying tDELAY by the number ofAD7280s in the daisychain. The total conversion time for all cell voltage and temperature conversions can be
calculated using the following equation: Total Conversion time = ((tACQ + tCONV) x (#conversions per part) - tACQ + (#parts x tDELAY) Where tACQ is the analog input acquisition time of the AD7280 as outlined in Table 7 tCONV is the conversion time of the AD7280 as outlined in Table 2 #conversions per part is 6, 9 or 12 as outlined in Table 6. #parts is the number of AD7280s in the daisychain
Rev. PrD | Page 15 of 33
06703-024
SCLK
AD7280
CNVST
Preliminary Technical Data
TOTAL CONVERSION TIME = ((tACQ + tCONV) x #conversions per part) - tACQ+ (#parts x tDELAY )
tCONV
INTERNAL ADC CONVERSIONS PART 1 VOLT 1 VOLT 2
tACQ + tCONV
VOLT 3 TEMP 6
tDELAY
INTERNAL ADC CONVERSIONS PART 2 VOLT 7
tDELAY
VOLT 8
VOLT 9
TEMP 12
tACQ + tCONV tDELAY tDELAY
VOLT 13 VOLT 14 VOLT 15 TEMP 18
INTERNAL ADC CONVERSIONS PART 3
tACQ + tCONV
Figure 14. ADC conversions & Readback on a chain of 3 AD7280s
Suggested External Component Configurations on Analog Inputs
As outlined in the Track-and -Hold section the acquisition time of the AD7280 is selected by the status of bits D6 and D5 in the CONTROL register. This provides flexibility in selecting external components on the analog inputs. Included below are two suggested configurations for placing external components on the analog inputs to the AD7280.
the 10k resistor. The cut off frequency of the low pass filter is 318Hz. Using these external components the default acquisition time of 400 ns may be used, which will allow a combined acquisition and conversion time of 1s.
Current Limiting Resistors
Please refer to Figure 16.
Combined LP filter and Current Limiting Resistors
Please refer to Figure 15.
10k Vin6 10k 10k Vin6 10k 10k 10k 10k 10k 10k 100nF Vin5 100nF Vin4 100nF Vin3 100nF Vin2 100nF Vin1 100nF Vin0 10k Vin0 10k Vin1 10k Vin2 10k Vin3 Vin5 10k Vin4
AD7280
AD7280
Figure 16. External Series Resistance
Figure 15. External Series Resistance & Shunt Capacitance
The 10k resistor in series with the inputs provides protection to the analog inputs in the event of an over-voltage or undervoltage on those inputs. The 100nF capacitor across the pseudo differential inputs acts as a low pass filter in conjunction with
The 10k resistor in series with the inputs provides protection to the analog inputs in the event of an over-voltage or undervoltage on those inputs. Using these external components an acquisition time of 1.6 s should be used, which will allow a combined acquisition and conversion time of 2.2s.
Rev. PrD | Page 16 of 33
Preliminary Technical Data
SELF TEST CONVERSION
A self-test conversion may be initiated on the AD7280 which allows the operation of the ADC to be verified. The self-test conversion is completed on the internal 1.2V bandgap reference voltage. The self-test conversion may be initiated on either a single AD7280 or on all AD7280s in the battery stack simultaneously. The conversion results may be read back though the read protocols defined in the Register map section. The self-test conversion may also be used to verify the operation of the ALERT outputs as described in the ALERT Output section.
AD7280
Vin6 Vin5 Vin4 10k 10k 10k 10k 100nF Vin3 100nF Vin2 100nF Vin1 100nF Vin0
AD7280
CONVERSION AVERAGING
The AD7280 includes an option where the ADC conversions completed on each cell input may be repeated with an averaged conversion result being stored in the individual register. The averaged conversion result may then be read back through the SPI interface in the same manner as a standard conversion result. The AD7280 may be programmed, through bits D10 and D9 of the CONTROL register, to complete 1, 2, 4 or 8 conversions. The default on power up is a single conversion.
Figure 17. Typical connections for a 4 cell application
CELL TEMPERATURE INPUTS
The AD7280 provides 6 single ended analog inputs, VT1 to VT6, to the ADC which may be used to convert the voltage output of a thermistor temperature measurement circuit. In the event that no temperature measurements are required, or that individual cell temperature measurements are not required the VT inputs may be used to convert any other 0 V to 5 V input signal. The AD7280 may be programmed to complete conversions on all 6 temperature channels, on 3 temperature channels (VT1, VT3 & VT5) or on none of the temperature input channels. The number of conversions is programmed through bits D15 and D14 of the CONTROL register. The number of conversions results supplied by the AD7280 for read back by the DSP/uP is programmed through bits D13 and D12 of the CONTROL register. In an application where the ALERT function is being used but only one or two temperature inputs are required the AD7280 should first be programmed to complete and readback only 3 temperature conversions, by setting bits D15 and D13 of the CONTROL register to 0, and bits D14 and D12 to 1. VT Channels VT5 and VT3 may be removed from the Alert detection by writing to bits D1 and D0 of the ALERT register. Please refer to ALERT Output section.
CONVERSION OF LESS THEN 6 VOLTAGE CELLS
The AD7280 provides 6 input channels for Battery Cell voltage measurement. The AD7280 may also be used in applications which require less then 6 voltage measurements. In these applications care should be taken to ensure that the sum of the individual cell voltages will still exceed the minimum VDD supply voltage. For this reason it is recommended that the minimum number of battery cells connected to each AD7280 is 4. Care should also be taken to ensure that the voltage on the Vin6 inputs is always greater than or equal to the voltage on the VDD supply pin. This design requirement is in place to allow the use of a diode on the VDD supply pin of the AD7280 which provides protection in the event of an open circuit in the battery stack. Even if a protection diode is not being used in the application the Vin6 input voltage must be greater than or equal to the VDD supply voltage. An example of the battery connections to the AD7280 in a 4 cell battery monitoring application is shown in Figure 17. Regardless of how many cell measurements are required in the user application the AD7280 will acquire and convert the voltages on all 6 voltage input channels. The conversion data on all 6 channels will be supplied to the DSP/uP using the SPI /Daisy Chain interfaces. The user should then ignore the conversion data which is not required in their application. If using the Alert function the user should program the Alert register to ensure that the shorted out channels do not incorrectly trigger an Alert output. Please refer to ALERT Output section.
Thermistor Termination Input
In the event that thermistors circuits are being used to measure each individual cell temperature the Thermistors Termination pin, VTTERM, may be used to the terminate the thermistor inputs for each cell temperature measurement. This reduces the termination resistor requirement from 6 resistors to 1. Bit D3 in the CONTROL register should be set to 1 when using the VTTERM input. It should be noted that, due to settling time requirements, the thermistor termination resistor option should only be used when the acquisition time of the AD7280 is set to its highest value, that is 1.6s. The acquisition time is configured by setting bits D6 and D5 of the CONTROL register as outlined in Table 7.
Rev. PrD | Page 17 of 33
AD7280
AD7280
VREG Rterm VTTERM VT1 VT2 VT3 VT4 VT5 VSS VT6
Preliminary Technical Data
POWER DOWN
The AD7280 provides a number of power down options. These may be described as follows:
* *
Full, or Hardware, Powerdown Software Powerdown
The AD7280 may be placed into full powerdown mode, which requires only 4uA max current, by taking the PD pin low. The falling edge of the PD pin will power down all analog and digital circuitry. The AD7280 may be placed into Software Power down mode, which requires only 1mA of current by setting bit D8 in the CONTROL register through the serial interface. When the AD7280 is powered down through the serial interface the regulator and the daisy chain circuitry stay powered up but the remaining analog and digital circuitry is powered down. This is necessary to ensure that the signal to power on the part, or series of parts, is correctly received. The AD7280 offers a PD TIMER register which allows the user to program a set time after which the AD7280 will go into power down. This will act as a time delay between the falling edge of the PD input, or the setting of bit D8 in the CONTROL register, and the AD7280 powering down. The PD Timer can be set to a value between 0 and 31 minutes, with a resolution of 1 minute. The user should first write to the PD TIMER register, to define the desired delay. Any subsequent falling edge on the PD input or setting of bit D8 the CONTROL register, will start the PD timer and after the programmed time will place the AD7280 into powerdown. The default value of the PD TIMER register on power up is 0h.
Figure 18. Typical Circuit using the Thermistor Termination Resistor
In the example shown the termination resistor is placed between the source voltage and the thermistor in the thermistor circuit. The VTTERM input may be used to terminate the thermistor inputs to either high or low voltage of the Thermistor circuit.
POWER REQUIREMENTS
The current consumed by the AD7280 in normal operation, that is when not in powerdown mode, is dependant on the mode in which the part is being operated. In a typical Lithium Ion battery monitoring application there are 3 distinct modes of operation. These can be described as follows:
* * *
Voltage and Temperature Conversion AD7280 Configuration & Data Readback Cell Balancing
The AD7280 consumes its highest level of current while converting voltage and/or temperature inputs to digital outputs. Depending on the configuration of the AD7280 the conversion time can be as little as 6us. As outlined in Table 1 the typical current required by the AD7280 during conversion is 7mA. When configuring the chain of AD7280s or when reading back the voltage and/or temperature conversion results from a chain of AD7280s the current required for each AD7280 is typically 4mA, as outlined in Table 1. The time required to read back the voltage conversions results from 96 Lithium Ion cells will depend on the speed of the interface clock used, that is SCLK, but it can be as low as 2.5ms. The typical current consumed by the AD7280 when the cell balancing outputs are switched on is 1mA. The duration of the Cell Balance outputs on time is defined by the user. When the AD7280 is not being used in any of the above modes of operation it is recommended that the AD7280 be powered down, as outlined below. This will significantly reduce the current draw by each AD7280 on the chain which will avoid unnecessary draining of the Lithium Ion cells.
POWER UP TIME
As outlined in the Power Down section a full power down of the AD7280, that is an active low on the PD input will power down all analog and digital circuitry. The recommended power up time for the internal reference, when decoupled with a 10F capacitor, is 5ms. It is recommended that no conversions be completed until the 5ms power up time has elapsed as it may result in inaccurate data.
CELL BALANCING OUTPUTS
The AD7280 provides 6 CB outputs which can be used to drive the gate of external transistors as part of a cell balancing circuit. Each CB output may be set to provide either a 0V or 5V output with respect to the absolute amplitude of the negative terminal of the battery cell which is being balanced. For example, the CB6 output will provide a 0V or 5V output with respect to the voltage on the Vin5 analog input. The CB outputs are set by writing to the CELL BALANCE register. The default value of the CELL BALANCE register on power up is 0h. In an application which daisychains a number of AD7280s
Rev. PrD | Page 18 of 33
Preliminary Technical Data
together it is recommended that series resistors be placed between the CB outputs of the AD7280 and the gates of the external Cell Balancing transistors. These are recommended to protect the AD7280s in the event that the external cell balancing transistors are damaged during the initial connection of the monitoring circuitry to the battery stack. An example of how this could occur would be a connection sequence which first provides the system ground, that is the ground supply to the master AD7280 on the daisychain, followed by a connection from any of the battery cells at a potential high enough to exceed the VGS of the cell balancing transistor, for example 40V. If these two connections are the only battery connections made in the system then this will result in 40V being applied to one of the Vin pins of the AD7280, which is also connected to the source input of one of the cell balancing transistors. However, because no power has been supplied to the VDD pin of the AD7280 all the CB outputs will be 0V. This will result in a reverse voltage of 40V across the VGS of the external transistor which may damage the device. In the event that the external transistor is damaged, the AD7280 may be protected by the use of 10kOhm series resistors on each of the CB output pins. Consideration should also be given to the protection of these external transistors during the initial connection of the monitoring circuitry to the battery stack.
Vin6 10k CB6 Vin5
AD7280
before powering down the AD7280. If no power down timer has been set, that is if the PD TIMER register is at its default value of 0h, then a falling edge on the PD pin, or the setting of bit D8 in the CONTROL register to 1, will switch off the CB outputs and power down the AD7280. If a power down time has been set the CB outputs will be powered down when the programmed power down timer has elapsed and the AD7280 is powered down.
ALERT OUTPUT
The Alert output on the AD7280 may be used to indicate if any of the following faults have occurred:
* * * *
Over-Voltage Under-Voltage Over-Temperature Under-Temperature
Following each completed conversion the cell voltage and temperature measurement results are compared to the fault thresholds. The fault thresholds can be set by writing to the OVER VOLTAGE. UNDER VOLTAGE, OVER TEMP and UNDER TEMP registers. An ALERT output is generated if the cell voltage or temperature results are outside the programmed fault thresholds. The Alert output can be defined as a static or a dynamic output, this is set by writing to the ALERT register. The static Alert output is a high signal which is pulled low in the event of a over or under voltage or temperature. The dynamic Alert is a square wave which can be programmed to a frequency of 100Hz or 1kHz. The Alert output may be used as part of a daisy chain in which case the AD7280 at the top of the chain, that is furthest away from the DSP/P should be programmed to generate the initial Alert output and each AD7280 in the chain will either pass that output through or pull the Alert signal low to indicate that there is a fault with that particular device. At the end of the daisy chain the master AD7280, that is the AD7280 which is connected to the DSP/P will take the Alert signal from the chain and pass it, in standard digital voltage format to the DSP/P. The functionality of the fault detection circuit, which generates the Alert output may be programmed through bits D7 to D4 of the ALERT register. As outlined previously (See Conversion of less then 6 Voltage cells) some applications may require less than 6 voltage measurements. As shown in Figure 17 it is recommended that the channels which are not being used on the AD7280 be shorted to the channel below them. To prevent the incorrect triggering of the Alert output in this application the AD7280 allows the user to select up to 2 voltage channels which may be taken out of the fault detection circuit. This may be
10k
CB5 Vin4
10k
AD7280
CB4 Vin3
10k
CB3 Vin2
10k
CB2 Vin1
10k
CB1 Vin0
Figure 19. Cell Balancing Configuration
The AD7280 offers 6 Cell Balance timer registers which allow the on-time of each CB output to be programmed. These are referred to as the CB TIMER registers. The CB timers can be set to a value between 0 and 30 minutes. The resolution of the CB Timer is 1 minute. At the end of the programmed CB Time the 6 CB outputs will return to their default state of 0V. The default value of the CB TIMER registers on power up is 0h. As noted in the Power Down section a power down timer may be programmed to allow cell balancing to occur for a set time
Rev. PrD | Page 19 of 33
AD7280
programmed through bits D3 and D2 of the ALERT register.
Table 8.ALERT Register settings
D7 to D6 00 01 D5 to D4 XX XX D3 to D0 XXXX XXXX AD7280 Action No Alert signal generated or passed [Default] Generates static [High] Alert signal to be passed down the Daisy Chain Generates 100Hz Square wave Alert signal to be passed down the Daisy Chain Generates 1kHz Square wave Alert signal to be passed down the Daisy Chain Reserved Reserved Passes Alert signal from AD7280 at higher potential in Daisy Chain AD7280 Action Includes all 6 Voltage channels in Alert detection [Default] XXXX XXXX XXXX XXXX 01 10 11 XX
Preliminary Technical Data
XX XX XX 00 Removes Vin5 from Alert detection Removes Vin5 & Vin4 from Alert detection Reserved Includes all 6 Temperature channels in Alert detection [Default] Removes VT5 from Alert detection Removes VT5 & VT3 from Alert detection
10
00
XXXX
XXXX XXXX
XX XX
01 10
10
01
XXXX
10 10 11
10 11 XX
XXXX XXXX XXXX
D7 to D4 XXXX
D3 to D2 00
D1 to D0 XX
The operation of the ALERT output can be verified by initiating a Self-Test conversion. The self-test conversion will convert a known voltage, 1.2V, which will trigger an ALERT output if the under voltage fault threshold is higher than 1.25V. To test the ALERT output the self-test should be initiated on the AD7280 furthest away from the DSP/P. This allows the ALERT path through each AD7280 to be verified. The remaining AD7280s in the battery stack should be placed into software powerdown to ensure that only the part which is converting the self-test voltage may generate an ALERT output.
Rev. PrD | Page 20 of 33
Preliminary Technical Data REGISTER MAP
Table 9.
Register Name CELL VOLTAGE 1 CELL VOLTAGE 2 CELL VOLTAGE 3 CELL VOLTAGE 4 CELL VOLTAGE 5 CELL VOLTAGE 6 CELL TEMP 1 CELL TEMP 2 CELL TEMP 3 CELL TEMP 4 CELL TEMP 5 CELL TEMP 6 SELF TEST CONTROL OVER VOLTAGE UNDER VOLTAGE OVER TEMP UNDER TEMP ALERT CELL BALANCE CB TIMER 1 CB TIMER 2 CB TIMER 3 CB TIMER 4 CB TIMER 5 CB TIMER 6 PD TIMER READ Register Address 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch Register Data D11 to D0 D11 to D0 D11 to D0 D11 to D0 D11 to D0 D11 to D0 D11 to D0 D11 to D0 D11 to D0 D11 to D0 D11 to D0 D11 to D0 D11 to D0 D15 to D8 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 Read/Write Register Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
AD7280
D15 and D14 of the CONTROL register to 11. The user should then pulse the CNVST input or complete a software convert start through the CS input. The conversion result is in 12-bit natural binary format.
CONTROL REGISTER
Table 13. 16-Bit Register
Dh Eh D15 to D8 D7 to D0 Read/Write Read/Write
The CONTROL register is an 16-bit register that sets the AD7280 Control modes.
Table 14. 16-Bit Register
D15 to D14 Select Conversion Inputs 00 = 6 Voltage & 6 Temp 01 = 6 Voltage & Temp 1,3 &5 10 = 6 Voltage only 11 = ADC Self Test Read Conversion Results 00 = 6 Voltage & 6 Temp 01 = 6 Voltage & Temp 1,3 &5 10 = 6 Voltage only 11 = No Read operation Conversion Start Format 0 = Falling edge of CNVST input 1 = Rising edge of CS Conversion Averaging 00 = Single Conversion only 01 = Average by 2 10 = Average by 4 11 = Average by 8 Powerdown format 0 = Falling edge of PD input 1 = Software PD Software Reset 0 = Bring out of Reset 1= Reset AD7280 Set Acquisition Tme 00 = Acquisition time 400ns 01 = Acquisition time 800ns 10 = Acquisition time 1.2us 11 = Acquisition time 1.6us Reserved; set to 1 Thermistor Termination Resistor 0 = Function not in use 1 = Termination resistor connected Reserved; set to 1
D13 to D12
D11
D10 to D9
D8
D7
CELL VOLTAGE REGISTERS
Table 10. 12-Bit Registers
0h to 5h D11 to D0 Read/Write D6 to D5
The CELL VOLTAGE registers store the conversion result from each cell input. The conversion result is in 12-bit natural binary format.
CELL TEMPERATURE REGISTERS
Table 11. 12-Bit Register
6h to Bh D11 to D0 Read/Write
D4 D3
The CELL TEMP registers store the conversion result from each temperature input. The conversion result is in 12-bit natural binary format.
D2 to D0
Select Conversion Inputs
Bits D15 and D14 of the CONTROL register determine which cell voltages and temperatures are converted following a CNVST pulse or the setting of the CNVST bit, D11, in the CONTROL register. The default value of D15 and D14 on power up are 00.
SELF-TEST REGISTER
Table 12. 12-Bit Register
Ch D11 to D0 Read/Write
The SELF-TEST register stores the conversion result of the ADC self-test. A self-test conversion is initiated by setting bits
Rev. PrD | Page 21 of 33
AD7280
Read Conversion Results
Bits D13 and D12 of the CONTROL register determine which cell voltages and temperatures conversion results are supplied to the serial or Daisychain data outputs pins for readback. The default value of D15 and D14 on power up are 00.
Fh
Preliminary Technical Data
OVER VOLTAGE REGISTER
Table 16. 8-Bit Register
D7 to D0 Read/Write
Conversion Start Format
The AD7280 offers two methods of initiating a conversion, the hardware CNVST pin or the software CS input. Bit D11 of the CONTROL register determines whether a conversion is initiated on the falling edge of the CNVST input or on the rising edge of the CS input. The default format on power up is the CNVST pin.
The OVERVOLTAGE THRESHOLD register determines the high voltage threshold of the AD7280. Cell voltage conversions which exceed the Over Voltage threshold trigger the ALERT output. The AD7280 allows the user to set the Over Voltage threshold to a value between 1V and 5V. The resolution of the Over Voltage threshold is 8-bits, that is 16mV. The default value of the Over Voltage threshold on power up is TBD mV.
UNDER VOLTAGE REGISTER
Table 17. 8-Bit Register
10h D7 to D0 Read/Write
Conversion Averaging
Bits D10 and D9 of the CONTROL register determines the number of conversions completed on each input with the average result being stored in the Result registers. The default value of the Conversion Averaging bits is 00, that is no averaging.
Powerdown Format
Bit D8 of the CONTROL register allows the AD7280 be placed into a software powerdown. Pleas refer to the Power Down section of more details. The default format on power up is the PD pin.
The UNDER VOLTAGE THRESHOLD register determines the low voltage threshold of the AD7280. Cell voltage conversions lower than the Under Voltage threshold trigger the ALERT output. The AD7280 allows the user to set the Under Voltage threshold to a value between 1V and 5V. The resolution of the Under Voltage threshold is 8-bits, that is 16mV. The default value of the Under Voltage threshold on power up is TBD mV.
OVER TEMP REGISTER
Table 18. 8-Bit Register
11h D7 to D0 Read/Write
Software Reset
Bit D7 of the CONTROL register allows the user to initiate a software Reset of the AD7280. Two write commands are required to complete the reset operation. Bit D7 must be set high to put the AD7280 into Reset. Bit D7 must then be set low to bring the AD7280 out of Reset.
Select Acquisition Time
Bits D6 and D5 of the CONTROL register determine the Acquisition time of the ADC. Please refer to the Track-andHold section for further detail. The default value of the Conversion time setting is 00.
Table 15.Analog Input Acquisition Time.
D6 to D5 00 01 10 11 Acquisition Time 400 ns 800 ns 1.2 s 1.6 s
The OVER TEMP THRESHOLD register determines the high temperature threshold of the AD7280. Cell temperature conversions which exceed the Over Temp threshold trigger the ALERT output. The AD7280 allows the user to set the Over Temperature threshold to a value between 0V and 5V. The resolution of the Over Temperature threshold is 8-bits, that is 19mV. The default value of the Over Voltage threshold on power up is TBD mV.
UNDER TEMP REGISTER
Table 19. 8-Bit Register
12h D7 to D0 Read/Write
Thermistor Termination Resistor
Bit D3 of the CONTROL register should be set if the user wishes to use a single thermistor termination resistor on the VTTERM pin. It should be noted that, due to settling time requirements, the thermistor termination resistor option should only be used when the acquisition time of the AD7280 is set to its highest value, that is 1.6s.
The UNDER TEMP THRESHOLD register determines the low temperature threshold of the AD7280. Cell temperature conversions lower than the Under Voltage threshold trigger the ALERT output. The AD7280 allows the user to set the Under Temperature threshold to a value between 0V and 5V. The resolution of the Under Voltage threshold is 8-bits, that is 19mV. The default value of the Under Voltage threshold on power up is TBD mV.
ALERT REGISTER
Table 20. 8-Bit Register
13h D7 to D0 Read/Write
The ALERT register determines the configuration of the ALERT function. The ALERT can be configured to be a static signal or a square wave. The static signal can be programmed to be either high or low. The frequency of the square wave can be set to either 100Hz or 1kHz. When a number of AD7280s are
Rev. PrD | Page 22 of 33
Preliminary Technical Data
operating in daisy chain mode the ALERT configuration is set on the AD7280 furthest away from the uP or DSP only. The ALERT registers on the remaining AD7280s in the chain should be programmed to pass the ALERT signal through the chain. Each of these parts will pass the static or dynamic ALERT signal through the chain or pull the signal low to indicate that an over/under voltage or over/under temperature has occurred.
Table 21.ALERT Register settings
D7 to D6 00 01 D5 to D4 XX XX D3 to D0 XXXX XXXX AD7280 Action No Alert signal generated or passed [Default] Generates static [High] Alert signal to be passed down the Daisy Chain Generates 100Hz Square wave Alert signal to be passed down the Daisy Chain Generates 1kHz Square wave Alert signal to be passed down the Daisy Chain Reserved Reserved Passes Alert signal from AD7280 at higher potential in Daisy Chain AD7280 Action Includes all 6 Voltage channels in Alert detection [Default] Removes Vin5 from Alert detection Removes Vin5 & Vin4 from Alert detection Reserved Includes all 6 Temperature channels in Alert detection [Default] Removes VT5 from Alert detection Removes VT5 & VT3 from Alert detection D3 0 = output off 1 = output on Set CB4 output 0 = output off 1 = output on Set CB3 output 0 = output off 1 = output on Set CB3 output 0 = output off 1 = output on Set CB1 output 0 = output off 1 = output on Reserved, set to 0
AD7280
D5
D4
D2
10
00
XXXX
D1-D0
10
01
XXXX
CB TIMER REGISTERS
Table 24. 8-Bit Register
15h to 1Ah D7 to D0 Read/Write
10 10 11
10 11 XX
XXXX XXXX XXXX
The CB TIMER registers allow the user to program individual ON times for each of the Cell Balance outputs. The AD7280 allows the user to set the CB Timer to a value between 0 and 30 minutes. The resolution of the CB Timer is 1 minute. The default value of the CB TIMER registers on power up is 0h.
Table 25. CB Timer register settings
D7-D3 D2-D0 5-bit binary code to set CB timer to value between 0 and 30 minutes Reserved, set to 0
D7 to D4 XXXX
D3 to D2 00
D1 to D0 XX
XXXX XXXX XXXX XXXX
01 10 11 XX
XX XX XX 00
PD TIMER REGISTER
Table 26. 8-Bit Register
1Bh D7 to D0 Read/Write
XXXX XXXX
XX XX
01 10
CELL BALANCE REGISTER
Table 22. 8-Bit Register
14h D7 to D0 Read/Write
The PD TIMER register determines the elapsed time before the AD7280 is automatically powered down. The AD7280 allows the user to set the PD Timer to a value between 0 and 31 minutes. The resolution of the PD Timer is 1 minute. When using the PD timer in conjunction with the CB timers the value programmed to the PD Timer should exceed that programmed to the CB Timer by at least 1 minute. The default value of the PD TIMER registers on power up is 0h.
Table 27. PD Timer register settings
D7-D3 D2-D0 5-bit binary code to set PD timer to value between 0 and 31 minutes Reserved, set to 0
The CELL BALANCE register determines the status of the 6 Cell Balance outputs. The six CB outputs are set by writing to bits D7 to D2 of the Cell Balance register. The default value of the Cell Balance register on power up is 0h.
Table 23. Cell Balance register settings
D7 Set CB6 output 0 = output off 1 = output on Set CB5 output
D6
Rev. PrD | Page 23 of 33
AD7280
READ REGISTER
Table 28. 8-Bit Register
1Ch D7 to D0 Read/Write
Preliminary Technical Data
The READ register, in conjunction with bits D13 and D12 of the CONTROL register and bit D3 of the write operation define the read operations of the AD7280. To read back a single register from the AD7280 the register address should be first written to the Read register. To read back a series of conversion results from the AD7280 an address of 0h should be written to the Read register. The default value of the READ register on power up is 0h.
Table 29. Read register settings
D7-D2 D1-D0 6-bit binary address for the register to be read Reserved, set to 0
Rev. PrD | Page 24 of 33
Preliminary Technical Data SERIAL INTERFACE
The AD7280's serial interface consists of four signals; CS, SCLK, SDIN and SDOUT. The SDIN line is used for transferring data into the on chip registers while the SDOUT line is used for reading the conversion results from the ADCs. SCLK is the serial clock input for the device, and all data transfers, either on SDIN or on SDOUT, take place with respect to SCLK. Data is clocked into and out of the AD7280 on the SCLK falling edge. The CS, input is used to frame the serial data being transferred to or from the device. CS, can also be used to initiate the sequence of conversions. In a Li-Ion Battery Monitoring application up to50 AD7280's may be daisy chained together to allow up to 300 individual LiIon cell voltages to be monitored. Each write operation must therefore include Device Address and Register Address in addition to the data to be written. An additional identifier bit is also required when addressing all AD7280s in the Daisy Chain. The AD7280 SPI Interface, in combination with the Daisy Chain Interface, allows any register in the 50 x AD7280 stack to be updated using one 24-bit write cycle.
Table 30. 24-Bit Write Cycle
Device Address1 D23-D18 Register Address D17-D12 Data D11- D4 Address All Parts D3 Additional Zero's D2-D0
AD7280
*
Register Data Read
The data returned from a conversion result read operation includes the Device Address and Channel Address information in addition to the 12-bits of conversion data. The data returned from a Register Data read operation includes the Device Address and Register Address in addition to the 8-bits of register data. The AD7280 SPI Interface, in combination with the Daisy Chain Interface, allows the conversion results of any AD7280 in the 50 x AD7280 stack to be read back using an N x 24-bit read cycle, where N is defined by the number of conversions completed on that part, that is 12, 9 or 6 (Please refer to Table 6). The user has the option of taking CS low for the duration of the N x 24 bit read cycle, or may pulse CS low for each individual 24-bit read cycle, that is N 24-bit wide CS frames.
Table 31. 24-Bit Read Conversion result Cycle
Device Address2 D23-D18 Device Address2 D23-D18 Channel Address D17-D14 Register Address D17-D12 Conversion Data D13-D2 Register Data D11-D4 2bit CRC D1-D0 2-bit CRC D1-D0
Table 32. 24-Bit Read Register Data Cycle
Zero D3-D2
There are two different types of read operation for the AD7280.
*
Conversion Results Read
Figure 20 shows the timing diagram for the serial interface of the AD7280. Please refer to the Daisy Chain Interface section for further information on the Daisy Chain Interface.
1
Device Address should be written LSB first. For example, to address device #1 the sequence of bits input to the AD7280 should be 100000. The Register Address and Data bits are input MSB first.
2
Device Address is read out LSB first. The Register Address, Channel Address and all Data bits are read out MSB first.
CS
t2
SCLK 1 2 3 4
t8 t9
t10
24
t3
SDO THREESTATE SDI MSB MSB-1
t6
t7
t11
LSB THREE-STATE
06703-027
t4
MSB MSB-1
t5
LSB
Figure 20. Serial Interface Timing Diagram
Rev. PrD | Page 25 of 33
AD7280
Cyclic Redundancy Check
The AD7280 SPI output includes a 2-bit Cyclic Redundancy Check (CRC) on the output data. This CRC may be used to detect any alteration in the data during transmission. The principle of a cyclic redundancy check is that the output data, to be transmitted, is divided by a fixed polynomial, the remainder of this mathematical operation is then attached to the output data and forms parts of the transmission. At the receiving end the user should complete the same mathematical operation on the data received. This will allow the user to confirm that the data which they have received is the same as the data which was originally transmitted. The 2-bit CRC, offered by the AD7280, will allow errors bursts of up to 2 bits to be detected. It will also detect up to 75% of errors bursts which are greater than 2 bits. The polynomial used by the AD7280 to calculate the CRC bits is x2 + 1. Data bits D17 to D2 of the 24-bit serial output are divided by this polynomial and the 2 bit remainder, following the division, becomes the CRC bits, D1 and D0, of the 24-bit serial output. On the AD7280 this division is implemented using the digital circuit outlined in Figure 21. For (i = 0; I < 16; i++) { shift2 = shift1;
Preliminary Technical Data
shift1 = xor_output; if (shift2 == 1) { if (Data_D17toD2[i] == 1) {xor_output = 0;} else {xor_output = 1;} } else { xor_output = Data_D17toD2[i]; }
D D17-D2
Q
D
Q
}
CRC[0] = D0
CRC[1] = D1
CRC Example 1
Reading a conversion result of A79h fromVin6 on device 0. Device Address : 000000 Channel Address : 0101 Conversion Data : 101001111001 Only the channel address and the conversion data are used for the calculation of the CRC. The data inputs to the CRC algorithm would be 0101101001111001. Each step of the calculation, from i=0 to i=15, is outlined in Table 33. Following the completion of the calculation the values of CRC1[D1]and CRC0[D0] may be read from the table as follows: CRC1 [D1] = Shift1 = 0 CRC0 [D0] = Xor_output = 1
Figure 21. CRC Implementation
The following pseudo code may be used to calculate the CRC. First the following variables need to be declared: 1. Data_D17toD2 - Data bits D17 to D2 of the 24-bit serial output. When reading a conversion result D17 to D2 includes the 4-bit channel address and the 12-bit conversion result. This data supplies one of the inputs to the XOR gate. 2. xor_output - integer variable. This will be the output of the XOR gate 3. shift1 - integer variable. This will be the output of the first shift register 4. shift2 - integer variable. This will be the output of the second shift register, which is in turn one of the inputs to the XOR gate 5. i - integer variable With the exception of variable Data_D17toD2 all variables should be initialised to zero. The following code will then implement the CRC calculation as outlined in Figure 21 above.
CRC Example 2
Reading the OverVoltage register, Fh, of Device 1 Device Address : 000001 Register Address : 001111 Register Data : 11001010
Rev. PrD | Page 26 of 33
Preliminary Technical Data
The register address, the register data and 2 additional zero's are used for the calculation of the CRC. The data inputs to the CRC algorithm would be 0011111100101000. Each step of the calculation, from i=0 to i=15, is outlined in Table 34. Following the completion of the calculation the values of CRC1[D1]and CRC0[D0] may be read from the table as follows: Table 33. CRC Example 1
CRC Calculation Steps D17toD2 Xor_output Shift1 Shift2 CRC Calculation Steps D17toD2 Xor_output Shift1 Shift2 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 2 0 0 1 0 2 1 1 0 0 3 1 0 0 1 3 1 1 1 0 4 1 1 0 0 4 1 0 1 1 5 0 0 1 0 5 1 0 0 1 6 1 0 0 1 6 1 1 0 0 7 0 0 0 0 7 1 1 1 0 8 0 0 0 0 8 0 1 1 1
AD7280
CRC1 [D1] = Shift1 = 1 CRC0 [D0] = Xor_output = 1
9 1 1 0 0 9 0 1 1 1
10 1 1 1 0 10 1 0 1 1
11 1 0 1 1 11 0 1 0 1
12 1 0 0 1 12 1 1 1 0
13 0 0 0 0 13 0 1 1 1
14 0 0 0 0 14 0 1 1 1
15 1 1 0 0 15 0 1 1 1
Table 34. CRC Example 2
It should be noted that on receipt of a transmission which includes a cyclic redundancy check the user has 2 options. The CRC calculation may be completed on the received portion of the data which was used to generate the original CRC bits. This will allow the user to verify that the CRC bits received in the transmission are the same as those calculated based on the received data. Another option which is offered by the Cyclic Redundancy Check is that the user may complete the CRC calculation on the entire data set i.e. the transmitted data and
the transmitted CRC. A feature of the redundancy check is that this operation will result in a remainder of zero if the data has been received correctly. Table 35 shows a repeat of CRC Example 1 with 2 additional steps which allows the full transmission to be decoded. As can be seen this results in zero outputs on the Shift1 and Xor_output variables.
Table 35. Repeat of CRC Example 1 with transmitted CRC bits included in calculation
CRC Calculation Steps D17toD0 Xor_output Shift1 Shift2 0 0 0 0 0 1 1 1 0 0 2 0 0 1 0 3 1 0 0 1 4 1 1 0 0 5 0 0 1 0 6 1 0 0 1 7 0 0 0 0 8 0 0 0 0 9 1 1 0 0 10 1 1 1 0 11 1 0 1 1 12 1 0 0 1 13 0 0 0 0 14 0 0 0 0 15 1 1 0 0 16 0 0 1 0 17 1 0 0 1
Rev. PrD | Page 27 of 33
AD7280
DAISY CHAIN INTERFACE
In a Li-Ion Battery Monitoring application up to 50 AD7280's may be daisy chained together to allow up to 300 individual LiIon cell voltages to be monitored. Each AD7280 is capable of monitoring up to 6 Li-Ion cells and is powered from the top and bottom voltage of the 6 Li-Ion cells. As a result the supply voltages of each AD7280 are offset by up to 30V from adjacent AD7280's in the chain. For this reason a standard Serial Interface Daisy Chain method cannot be used. The AD7280 includes a Daisy Chain Interface separate to the standard SPI interface. This Daisy Chain interface allows each AD7280 in the chain to relay data to and from adjacent AD7280's. In addition to the standard wire SPI the AD7280 serial interface include 3 optional interface pins, ALERT, CNVST and PD. Each input and output pin on the 7 wire interface requires at least one additional I/O for the Daisy Chain Interface, that is to allow the information to passed to an AD7280 operating at a higher supply voltage. The SDO and ALERT outputs will also require a further daisy chain pin to allow the information to be passed to an AD7280 operating at a lower supply voltage. The remaining 5 interface pins, CS, SCLK, SDI, CNVST and PD do not require additional pins to pass information to a AD7280 operating at a lower voltage as each of these input pins can operate as both SPI inputs or Daisy Chain inputs. Their functionality is defined by the state of the Master pin. The MASTER pin on the AD7280 at the base of the Daisy Chain should be set high, tied to VDD supply, to ensure that this device interfaces to the DSP or Processor using the standard Serial Interface. The MASTER pin on the remaining AD7280s in the Daisy Chain should each be connected to their respective VSS pins which disables the serial interface pins on those devices. This allows the CS, SCLK, SDI, CNVST and PD inputs, in addition to the SDOlo and ALERTlo outputs, to pass signals to and from an AD7280 operating at a lower potential. As explained in the Serial Interface section only one 24-bit write cycle is required to write to any register in the 50 x AD7280 stack . To read back the conversion data from all channels monitoring the battery stack requires only a (24 x N)-bit read cycle where N is the number of channels in the battery stack. Note: this is the default read configuration on power up. If the settings of the Read or control registers have been changed then additional write cycles may be required. The recommended SCLK frequency to ensure correct operation of the Daisy Chain Interface is 1MHz. With a 1MHz SCLK it will take ~2.34 ms to read back the voltage conversions on 96 channels.
Preliminary Technical Data
chain of AD7280's the Device Address corresponds to the position of the individual AD7280 in the chain with respect to the device acting as Daisy Chain Master, that is the device connected directly to the DSP/P. For example, in an application which uses 16 AD7280's to monitor 96 channels the device acting as Daisy Chain Master should be addressed with a Device Address of 00000, the 16th AD7280 in the chain should be addressed with a Device Address of 001111. Each individual AD7280 is preset with an address of zero, that is, 0h. When a write operation is initiated by the DSP or Processor the Daisy Chain Master compares the Device Address received with its own address. If the addresses do not match the AD7280 will decrement the Device Address by one, 1h, and the new Device Address will be passed to the next AD7280 in the chain with the remainder of the original 24-bit write. The second AD7280 will again compare the received Device Address with its own address, if the addresses do not match 1h will be subtracted from the Devices Address and again passed up the chain. This will continue until the received Device Address matches the preset address, 0h, and the write operation is completed. The same principle will apply when transferring data down the stack to the DSP or Processor. The Device Address supplied from each individual AD7280 will be incremented by one for each AD7280 it passes through on the chain. To write to the same register on all AD7280's in the stack bit D3 in the 24-bit write cycle should be set high. This will result in the 8-bit register data, bits D11-D4, are written to the same register address on all parts. The Device address, bits D23-D18, should be regarded as Don't Care bits when writing to all parts in the stack. For example when initiating a conversion on all AD7280s in the stack bit D3 should be set high, the Register address should be set to Dh, to address the CONTROL register and bit D11 of the 24-bit write cycle should be set high. This will initiate a conversion on the rising edge of CS, on all AD7280s in the stack.
Addressing the AD7280
As explained in the previous section all write operations to the AD7280 must include the Device Address and Register Address in addition to the data to be written. In any application using a
Rev. PrD | Page 28 of 33
Preliminary Technical Data READING DATA FROM THE AD7280
There are a number of read options available on the AD7280. The user may read back the results from all the conversions completed on an individual part in the chain, from all the conversions completed on all parts in the chain or from individual registers on selected parts in the chain. In each case the user is required to first write to the Read register on the selected parts to configure that part to supply the correct data on the outputs. When reading back an individual register result the address of that register should be written to the read register of the selected part. When reading back conversion results from any or all parts in the chain an address of 0h should be written to the read register of the selected parts. When the address written to the read register is 0h the conversion results selected for read back are controlled by setting bits D13 and D12 of the Control register. Please refer to Table 14. This allows the user to select 4 different read back options
AD7280
daisychain. Note: 0h is the default value of this register on power up and following a reset operation.
*
Write to the Control register on all parts. Set bits D15 and D14 to select the required conversions. Set bits D13 and D12 to select the required conversion results for read back. Initiate the conversions through either the falling edge of CNVST or the rising edge of CS. Allow sufficient time for each conversion to be completed. Please refer to Converting Cell Voltages and Temperatures section. Either bring CS low and apply 24 SCLKs for each conversion result to be read back or apply an individual CS pulse, each framing 24 SCLKs, for each conversion result to be read back.
* *
*
* * * *
Read back 12 conversion results: 6 voltage and 6 temperature Read back 9 conversion results: 6 voltage and 3 temperature Read back 6 conversion results: 6 voltage results only Switch off read operation on this part
The following section outlines ten examples of Conversion and /or Readback routines which would be commonly used in an application using a chain of AD7280s to monitor the voltage and/or temperature of the a stack of Lithium Ion batteries.
Convert and Read all parts, all voltages and all temperatures
* * * *
Register address 0h should be written to the Read register on all parts Bits D15-D12 of the CONTROL register should be set to 0 on all parts. Initiate conversion through either the falling edge of CNVST or the rising edge of CS. Following the completion of the conversion bring CS low and apply 24 SCLKs for each voltage and temperature result to be read back.
If the user wishes to read back the conversion results from a single AD7280 in the daisy chain bits D13 and D12 of the control register on that part should be set to select the correct conversion results. Bits D13 and D12 on all other AD7280s in the daisy chain should be set to switch off the read operation on those parts. It should be noted that it is more efficient in terms of 24-bit write cycles to first switch off the read operation on all AD7280s in the daisy chain. This can be achieved with a single write cycle, using bit D3 to address all parts in the chain. The user may then address the individual part and set bits D13 and D12 to select the required conversion results. When reading back conversion data from any, or all, of the AD7280s in a daisy chain the conversion results returned from the AD7280 will be the last completed conversion on that part. It is recommended that the user also set bits D15 and D14 of the control register, to select the number of conversions to be completed on each part, and initiate the conversions through either the CNVST pin or the rising edge of CS., as part of the read operation. This allows the user to implement a simple convert and read back routine with the most efficient number of 24-bit write and read operations. A general example of this routine, which would convert and read back from all parts in the AD7280 daisy chain would be:
Convert and Read all parts, all voltages and three temperatures per part
* *
Register address 0h should be written to the Read register on all parts Bits D15 and D13 of the CONTROL register should be set to 0, bits D14 and D12 should be set to 1 on all parts. Initiate conversion through either the falling edge of CNVST or the rising edge of CS. Following the completion of the conversion either bring CS low and apply 24 SCLKs for each conversion result to be read back or apply an individual CS pulse, each framing 24 SCLKs, for each conversion result to be read back.
* *
*
Write0h to the Read register on all of the parts in the
Rev. PrD | Page 29 of 33
AD7280
Convert and Read all parts, all voltages
* *
Register address 0h should be written to the Read register on all parts Bits D15 and D13 of the CONTROL register should be set to 1, bits D14 and D12 should be set to 0 on all parts. Initiate conversion through either the falling edge of CNVST or the rising edge of CS. Following the completion of the conversion either bring CS low and apply 24 SCLKs for each conversion result to be read back or apply an individual CS pulse, each framing 24 SCLKs, for each conversion result to be read back.
Preliminary Technical Data
pulse, each framing 24 SCLKs, for each conversion result to be read back.
Convert and Read one part, all voltages, no temperatures
* *
Register address 000000 should be written to the Read register of the part that is to be read Bits D13-D12 of the CONTROL register should be set to 1 on all parts. This switches off the read operation on all parts. Bit D14 and D12 of the CONTROL register of the part to be read from should be set to 0 and bits D15 and D13 should be set to 1. Initiate conversion through either the falling edge of CNVST or the rising edge of CS. Following the completion of the conversion either bring CS low and apply 24 SCLKs for each conversion result to be read back or apply an individual CS pulse, each framing 24 SCLKs, for each conversion result to be read back. The register address corresponding to the voltage or temperature result to be read should be written to the Read register of the part that is to be read, see Table 9 for register addresses. Bits D13-D12 of the CONTROL register should be set to 1 on all parts. This switches off the read operation on all parts. Bits D13 and D12 of the CONTROL register of the part to be read from should be set such that a conversion will be completed on the required channel. Note: With the exception of a Self-Test conversion it is not possible to convert on a single channel, 6, 9 or 12 conversions must be completed. Initiate conversion through either the falling edge of CNVST or the rising edge of CS. Following the completion of the conversion bring CS low and apply 24 SCLKs to be read back the desired voltage or temperature. The register address corresponding to the voltage or temperature result to be read should be written to the Read register of the part that is to be read, see Table 9 for register addresses. Bits D13-D12 of the CONTROL register should be set to 1 on all parts. This switches off the read operation on all parts.
* *
*
* *
Convert and Read one part, all voltages and all temperatures
* *
Register address 000000 should be written to the Read register of the part that is to be read Bits D13-D12 of the CONTROL register should be set to 1 on all parts. This switches off the read operation on all parts. Bits D15-D12 of the CONTROL register of the part to be read from should be set to 0. Initiate conversion through either the falling edge of CNVST or the rising edge of CS. Following the completion of the conversion either bring CS low and apply 24 SCLKs for each conversion result to be read back or apply an individual CS pulse, each framing 24 SCLKs, for each conversion result to be read back.
Convert and Read a single voltage or temperature result
*
* * *
*
*
Convert and Read one part, all voltages and temperatures 1, 3 & 5
* *
Register address 000000 should be written to the Read register of the part that is to be read Bits D13-D12 of the CONTROL register should be set to 1 on all parts. This switches off the read operation on all parts. Bit D15 and D13 of the CONTROL register of the part to be read from should be set to 0 and bits D14 and D12 should be set to 1. Initiate conversion through either the falling edge of CNVST or the rising edge of CS. Following the completion of the conversion either bring CS low and apply 24 SCLKs for each conversion result to be read back or apply an individual CS
* *
*
Read a single register
*
* *
*
Rev. PrD | Page 30 of 33
Preliminary Technical Data
* *
Bits D13 and D12 of the CONTROL register of the part to be read from should be set to 0. Bring CS low and apply 24 SCLKs to be read back the desired register. The register address corresponding to the self-test conversion, should be written to the Read register of all parts, see Table 9 for register addresses. Bits D15-D14 of the CONTROL register should be set to 1 on all parts to select the self-test conversion. Bits D13-D12 of the CONTROL register should be set to 1 on all parts. This switches off the read operation on all parts. Initiate conversion through either the falling edge of CNVST or the rising edge of CS. To read back the self-test conversion result from each individual part bits D13-D12 should be set to 0 for that part and the register data read back as outlined in Read a single register section. The self-test conversion results must be read back individually from each part. Bits D13-D12 of the CONTROL register should be set
AD7280
to 1 on all parts. This switches off the read operation on all parts.
*
Self-Test conversion, all parts
*
BitD8 in the CONTROL register of all parts should be set to 1 to put each part into a software power down. This prevents the ALERT function on the parts not undergoing a self-test conversion from being triggered. Bit D8 in the CONTROL register of the part for which a self-test conversion is requested should be set to 0. This bring this part out of powerdown. The register address corresponding to the self-test conversion, should be written to the Read register of the part under test, see Table 9 for register addresses. Bits D15-D14 of the CONTROL register should be set to 1 on the part under test to select the self-test conversion. Bits D13-D12 of the CONTROL register should be set to 0 the part under test. Initiate conversion through either the falling edge of CNVST or the rising edge of CS. the register data should be read back as outlined in Read a single register section.
*
* *
*
* *
*
* * *
Self-Test conversion, single part
*
Rev. PrD | Page 31 of 33
AD7280
OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
48 1
PIN 1
Preliminary Technical Data
9.20 9.00 SQ 8.80
37 36
1.45 1.40 1.35
TOP VIEW
0.20 0.09 7 3.5 0 0.08 COPLANARITY
(PINS DOWN)
7.20 7.00 SQ 6.80
0.15 0.05
12 13 24
25
SEATING PLANE
VIEW A
0.50 BSC LEAD PITCH
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 22. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters
7.00 BSC SQ
0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 23. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7280BSTZ1 AD7280DSTZ1 AD7280BCPZ1 AD7280DCPZ1 Temperature Range -40C to +85C -40C to +105C -40C to +85C -40C to +105C Package Description 48-Lead LQFP 48-Lead LQFP 48-Lead LFCSP 48-Lead LFCSP Package Option ST-48 ST-48 CP-48-1 CP-48-1
1
Z = Pb-free part.
Rev. PrD | Page 32 of 33
051706-A
VIEW A
0.27 0.22 0.17
Preliminary Technical Data
AD7280
(c) 2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07731-0-8/08(PrD)
Rev. PrD | Page 33 of 33

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